JPH064579Y2 - フレキシブルプリント配線板 - Google Patents

フレキシブルプリント配線板

Info

Publication number
JPH064579Y2
JPH064579Y2 JP15759587U JP15759587U JPH064579Y2 JP H064579 Y2 JPH064579 Y2 JP H064579Y2 JP 15759587 U JP15759587 U JP 15759587U JP 15759587 U JP15759587 U JP 15759587U JP H064579 Y2 JPH064579 Y2 JP H064579Y2
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
metal reinforcing
flexible printed
reinforcing layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP15759587U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0163136U (en]
Inventor
雅洋 海津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP15759587U priority Critical patent/JPH064579Y2/ja
Publication of JPH0163136U publication Critical patent/JPH0163136U/ja
Application granted granted Critical
Publication of JPH064579Y2 publication Critical patent/JPH064579Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
JP15759587U 1987-10-15 1987-10-15 フレキシブルプリント配線板 Expired - Lifetime JPH064579Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15759587U JPH064579Y2 (ja) 1987-10-15 1987-10-15 フレキシブルプリント配線板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15759587U JPH064579Y2 (ja) 1987-10-15 1987-10-15 フレキシブルプリント配線板

Publications (2)

Publication Number Publication Date
JPH0163136U JPH0163136U (en]) 1989-04-24
JPH064579Y2 true JPH064579Y2 (ja) 1994-02-02

Family

ID=31437172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15759587U Expired - Lifetime JPH064579Y2 (ja) 1987-10-15 1987-10-15 フレキシブルプリント配線板

Country Status (1)

Country Link
JP (1) JPH064579Y2 (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013084748A (ja) * 2011-10-07 2013-05-09 Murata Mfg Co Ltd 電子部品

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2634469B2 (ja) * 1989-11-27 1997-07-23 株式会社日立製作所 配線基板
JPH03239331A (ja) * 1990-02-16 1991-10-24 Matsushita Electron Corp 半導体装置の製造方法
JPH0727643Y2 (ja) * 1990-04-06 1995-06-21 日本アビオニクス株式会社 フレキシブル・リジッド・プリント配線板
JP3724920B2 (ja) * 1997-06-10 2005-12-07 日本特殊陶業株式会社 多層プリント配線板
JP3251930B2 (ja) * 1999-11-02 2002-01-28 日東電工株式会社 フレキシブル配線板
JP2003133653A (ja) * 2001-10-25 2003-05-09 Hitachi Ltd 配線基板およびそれを用いた半導体装置の実装構造体
JP2005183559A (ja) * 2003-12-18 2005-07-07 Nec Corp プリント配線板およびその製造方法
JP2007019078A (ja) * 2005-07-05 2007-01-25 Shindo Denshi Kogyo Kk フレキシブルプリント配線板、プリント回路板、およびフレキシブルプリント配線板の製造方法
JP2009166334A (ja) * 2008-01-15 2009-07-30 Seiko Epson Corp 液体噴射ヘッド及び液体噴射装置
JP4798237B2 (ja) * 2009-03-09 2011-10-19 株式会社デンソー Ｉｃ搭載基板、及び多層プリント配線板
WO2014203586A1 (ja) * 2013-06-19 2014-12-24 株式会社フジクラ 伸縮性基板、回路基板、及び伸縮性基板の製造方法
JP2015142051A (ja) * 2014-01-29 2015-08-03 住友電気工業株式会社 電子部品及び電子部品の製造方法
WO2015008671A1 (ja) * 2013-07-16 2015-01-22 住友電気工業株式会社 電子部品及び電子部品の製造方法
JP6783724B2 (ja) * 2017-08-22 2020-11-11 太陽誘電株式会社 回路基板
US10602608B2 (en) 2017-08-22 2020-03-24 Taiyo Yuden Co., Ltd. Circuit board
JP6644743B2 (ja) * 2017-08-22 2020-02-12 太陽誘電株式会社 回路基板及び半導体モジュール
JP6745770B2 (ja) 2017-08-22 2020-08-26 太陽誘電株式会社 回路基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013084748A (ja) * 2011-10-07 2013-05-09 Murata Mfg Co Ltd 電子部品

Also Published As

Publication number Publication date
JPH0163136U (en]) 1989-04-24

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